The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
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---- WISHBONE Wishbone_BFM IP Core ----
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---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
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---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specification document.
