Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標(biāo)簽： Creating Machines Mentor State
上傳時(shí)間： 2013-11-02
上傳用戶：xauthu
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過(guò)Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過(guò)下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中。 關(guān)鍵詞：Verilog HDL；硬件描述語(yǔ)言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
標(biāo)簽： Verilog HDL 多功能 數(shù)字
上傳時(shí)間： 2013-11-10
上傳用戶：hz07104032
Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
標(biāo)簽： EMI 開關(guān)電源 英文
上傳時(shí)間： 2013-11-16
上傳用戶：萍水相逢
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
西門子建筑電器-電氣安裝技術(shù)部發(fā)行的各類產(chǎn)品樣本：小型斷路器、剩余電流保護(hù)斷路器和模數(shù)化產(chǎn)品(中/ 英文)Miniature Circuit-Breakers, Residual Current Operated Circuit-Breakers and Modular Devices (Chinese/English)低壓熔斷器系統(tǒng)(中/ 英文)Fuse System (Chinese/English)雷擊，過(guò)電壓－不再是問(wèn)題(中文)Thunderstorms - no problem (Chinese)西門子建筑電器目錄(中文)Electrical Installation Technology Catalog (Chinese)終端配電保護(hù)產(chǎn)品(中文)5 IN 1 (Chinese)SIKUS 和 STAB UNIVERSAL 目錄(中文)SIKUS and STAB UNIVERSAL Catalogue (Chinese)SIKUS HC 目錄(中文)SIKUS HC Catalogue (Chinese)SentronTM 母線槽 (中文)SentronTM Busway System (Chinese)SentronTM 母線槽系統(tǒng)快速選型 (準(zhǔn)備中) (中文)SentronTM Busway System quick selection (in preparing) (Chinese)建筑低壓配電一體化解決方案－住宅小區(qū)應(yīng)用(中文)Building LV PD Solution (Chinese)西門子 DELTA vista“遠(yuǎn)景”系列開關(guān)和插座價(jià)目表(中文)Delta vista Switch and Socket Pricelist (Chinese)instabus EIB 面向未來(lái)的樓宇智能控制系統(tǒng)(中文)instabus EIB (Chinese)instabus EIB 面向未來(lái)的樓宇智能控制系統(tǒng)技術(shù)手冊(cè) (準(zhǔn)備中) (中文)instabus EIB technical handbook (in preparing) (Chinese)西門子電氣安裝技術(shù)業(yè)績(jī)卓越(中/ 英文)ET Reference Manual (Chinese/English)
上傳時(shí)間： 2013-11-23
上傳用戶：瓦力瓦力hong
在Multisim 10軟件環(huán)境下，設(shè)計(jì)一種由運(yùn)算放大器構(gòu)成的精確可控矩形波信號(hào)發(fā)生器，結(jié)合系統(tǒng)電路原理圖重點(diǎn)闡述了各參數(shù)指標(biāo)的實(shí)現(xiàn)與測(cè)試方法。通過(guò)改變RC電路的電容充、放電路徑和時(shí)間常數(shù)實(shí)現(xiàn)了占空比和頻率的調(diào)節(jié)，通過(guò)多路開關(guān)投入不同數(shù)值的電容實(shí)現(xiàn)了頻段的調(diào)節(jié)，通過(guò)電壓取樣和同相放大電路實(shí)現(xiàn)了輸出電壓幅值的調(diào)節(jié)并提高了電路的帶負(fù)載能力，可作為頻率和幅值可調(diào)的方波信號(hào)發(fā)生器。Multisim 10仿真分析及應(yīng)用電路測(cè)試結(jié)果表明，電路性能指標(biāo)達(dá)到了設(shè)計(jì)要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
標(biāo)簽： Multisim 矩形波 信號(hào)發(fā)生器 仿真
上傳時(shí)間： 2014-01-21
上傳用戶：shen007yue
本程序集是Allen I. Holub所寫的《Compiler Design in C》一書的附隨軟件，其中有作者自己編寫的詞法分析和語(yǔ)法分析工具LeX，occs和LLama，該軟件包還包括一個(gè)顯示C語(yǔ)言分析過(guò)程的程序
標(biāo)簽： I. Compiler Design Allen
上傳時(shí)間： 2014-01-08
上傳用戶：siguazgb
PGP Components使用PGP算法的加密控件。(有源代碼）工作在：D2 D3 D4 D5。作者：Michael in der Wiesche
標(biāo)簽： Components PGP Michael Wiesche
上傳時(shí)間： 2013-12-28
上傳用戶：koulian
a set of cross-platform tools that is useful for programming the GBA written in Java.
標(biāo)簽： cross-platform programming written useful
上傳時(shí)間： 2015-01-06
上傳用戶：yd19890720
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