Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
基于通用集成運(yùn)算放大器，利用MASON公式設(shè)計(jì)了一個(gè)多功能二階通用濾波器，能同時(shí)或分別實(shí)現(xiàn)低通、高通和帶通濾波，也能設(shè)計(jì)成一個(gè)正交振蕩器。電路的極點(diǎn)頻率和品質(zhì)因數(shù)能夠獨(dú)立、精確地調(diào)節(jié)。電路使用4個(gè)集成運(yùn)放、2個(gè)電容和11個(gè)電阻，所有集成運(yùn)放的反相端虛地。利用計(jì)算機(jī)仿真電路的通用濾波功能、極點(diǎn)頻率和品質(zhì)因數(shù)的獨(dú)立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the result shows that the presented circuit is valid and effective.
標(biāo)簽： MASON 多功能 二階 濾波器設(shè)計(jì)
上傳時(shí)間： 2013-10-09
上傳用戶：13788529953
Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable across platforms and network types
標(biāo)簽： cross-platform developers abstract library
上傳時(shí)間： 2015-01-14
上傳用戶：ghostparker
A Waiter relays an order Object to a Producer, waits in an independent thread during the production, and then delivers the result using a Consumer callback method.
標(biāo)簽： independent production Producer Waiter
上傳時(shí)間： 2015-02-10
上傳用戶：lepoke
High Performance MySQL (O Reilly,2004）
標(biāo)簽： Performance Reilly MySQL High
上傳時(shí)間： 2015-02-21
上傳用戶：nanfeicui
order發(fā)計(jì)算光子晶體的能帶結(jié)構(gòu)，比較好
上傳時(shí)間： 2014-01-24
上傳用戶：yimoney
NTL is a high-performance, portable C++ library providing data structures and algorithms for manipulating signed, arbitrary length integers, and for vectors, matrices, and polynomials over the integers and over finite fields.
標(biāo)簽： high-performance algorithms structures providing
上傳時(shí)間： 2014-01-05
上傳用戶：水中浮云
FlexCompress is a high-speed compression library developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption algorithms that allows you to integrate archiving or backup features into your programs in a fast and easy way.
標(biāo)簽： functionality FlexCompress compression high-speed
上傳時(shí)間： 2015-04-04
上傳用戶：s363994250
SR-tree is an index structure for high-dimensional nearest neighbor queries，C++ sourcecode. SR-tree outperforms the R*-tree and the SS-tree especially for high-dimensional and non-uniform data which are likely to appear in the actual image / video applications.
標(biāo)簽： high-dimensional structure neighbor SR-tree
上傳時(shí)間： 2013-12-10
上傳用戶：zjf3110
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