Introduce HIgh-Speed Digital System Design.
標簽： HIgh-Speed Digital Design System
上傳時間： 2013-10-20
上傳用戶：gps6888
The TJA1042 is a HIgh-Speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for HIgh-Speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： HIgh-Speed transce 1042 TJA
上傳時間： 2014-12-28
上傳用戶：氣溫達上千萬的
The TJA1051 is a HIgh-Speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for HIgh-Speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： HIgh-Speed transce 1051 TJA
上傳時間： 2013-10-17
上傳用戶：jisujeke
FlexCompress is a HIgh-Speed compression library developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption algorithms that allows you to integrate archiving or backup features into your programs in a fast and easy way.
標簽： functionality FlexCompress compression HIgh-Speed
上傳時間： 2015-04-04
上傳用戶：s363994250
Multicode HIgh-Speed Transmission for Wireless Mobile Communications
標簽： Communications Transmission HIgh-Speed Multicode
上傳時間： 2014-01-08
上傳用戶：GavinNeko
pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.
上傳時間： 2014-01-22
上傳用戶：曹云鵬
HSDPA（High Speed Downlink Packet Access）技術是WCDMA基于R5的增強型技術，通過各種 核心技術可使下行速率達到14.4M，是WCDMA移動運營商進行大流量移動多媒體服務的首選技術。 下面簡單介紹中興通訊的HSPDA解決方案... ...
標簽： Downlink Access Packet HSDPA
上傳時間： 2015-05-13
上傳用戶：頂得柱
Interfacing AD7276 HIgh-Speed Data Converters to ADSP-BF535 Blackfin Processors
標簽： Interfacing HIgh-Speed Converters Processors
上傳時間： 2013-12-20
上傳用戶：希醬大魔王
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標簽： integrating controller guidelines document
上傳時間： 2013-11-27
上傳用戶：電子世界
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標簽： integrating controller guidelines document
上傳時間： 2015-11-18
上傳用戶：xhz1993
