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Entity

  • 實現(xiàn)ORMapping

    實現(xiàn)ORMapping,利用Ado.net將數(shù)據(jù)庫中的表映射到Entity 實現(xiàn)對實體訪問的方式訪問數(shù)據(jù)庫;

    標簽: ORMapping

    上傳時間: 2013-12-25

    上傳用戶:moerwang

  • JAVA SMPP 源碼

    Introduction jSMPP is a java implementation (SMPP API) of the SMPP protocol (currently supports SMPP v3.4). It provides interfaces to communicate with a Message Center or an ESME (External Short Message Entity) and is able to handle traffic of 3000-5000 messages per second. jSMPP is not a high-level library. People looking for a quick way to get started with SMPP may be better of using an abstraction layer such as the Apache Camel SMPP component: http://camel.apache.org/smpp.html Travis-CI status: History The project started on Google Code: http://code.google.com/p/jsmpp/ It was maintained by uudashr on Github until 2013. It is now a community project maintained at http://jsmpp.org Release procedure mvn deploy -DperformRelease=true -Durl=https://oss.sonatype.org/service/local/staging/deploy/maven2/ -DrepositoryId=sonatype-nexus-staging -Dgpg.passphrase=<yourpassphrase> log in here: https://oss.sonatype.org click the 'Staging Repositories' link select the repository and click close select the repository and click release License Copyright (C) 2007-2013, Nuruddin Ashr uudashr@gmail.com Copyright (C) 2012-2013, Denis Kostousov denis.kostousov@gmail.com Copyright (C) 2014, Daniel Pocock http://danielpocock.com Copyright (C) 2016, Pim Moerenhout pim.moerenhout@gmail.com This project is licensed under the Apache Software License 2.0.

    標簽: JAVA SMPP 源碼

    上傳時間: 2019-01-25

    上傳用戶:dragon_longer

  • 源代碼LIBRARY IEEE USE IEEE

    通用寄存器的部分代碼 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL Entity traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic

    標簽: IEEE LIBRARY USE 源代碼

    上傳時間: 2020-03-25

    上傳用戶:lchen

  • VHDL4選1數(shù)據(jù)選擇器

    VHDL編寫的4選一數(shù)據(jù)選擇器 Entity mux41a is        port(a,b:in std_logic;                s1,s2,s3,s4:in std_logic;                y: out std_logic); end Entity mux41a; architecture one of mux41a is signal ab:std_logic_vector(1 downto 0);

    標簽: VHDL 數(shù)據(jù)選擇器

    上傳時間: 2020-05-15

    上傳用戶:cdga

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