參照棧類模板的例子編寫一個(gè)隊(duì)列類模板class <T> Queue，私有成員包括：隊(duì)首指針Front，隊(duì)尾指針Tail，隊(duì)列容積max。實(shí)現(xiàn)：構(gòu)造函數(shù)Queue，復(fù)制構(gòu)造函數(shù)Queue，析構(gòu)函數(shù)~Queue，入隊(duì)函數(shù)In，出隊(duì)函數(shù)Out（每次出隊(duì)，后面的元素自動(dòng)前移一位），判隊(duì)列空函數(shù)Empty。并分別用隊(duì)列類模板定義int和double對(duì)象，通過(guò)實(shí)例調(diào)用各個(gè)成員函數(shù)。
標(biāo)簽： Queue 函數(shù) double class Front Empty 隊(duì)列 Tail 模板 Out
上傳時(shí)間： 2020-05-04
上傳用戶：1qw2e3r4t5y6u7i8
Artificial Intelligence (AI) is a big field, and this is a big book. We have tried to explore the full breadth of the field, which encompasses logic, probability, and continuous mathematics; perception, reasoning, learning, and action; and everything from microelectronic devices to robotic planetary explorers. The book is also big because we go into some depth. The subtitle of this book is “A Modern Approach.” The intended meaning of this rather Empty phrase is that we have tried to synthesize what is now known into a common frame- work, rather than trying to explain each subfield of AI in its own historical context. We apologize to those whose subfields are, as a result, less recognizable.
標(biāo)簽： A-Modern-Approach Intelligence
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
FPGA片內(nèi)FIFO讀寫測(cè)試Verilog邏輯源碼Quartus工程文件+文檔說(shuō)明，使用 FPGA 內(nèi)部的 FIFO 以及程序?qū)υ?FIFO 的數(shù)據(jù)讀寫操作。FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時(shí)鐘 input rst_n //復(fù)位信號(hào)，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數(shù)據(jù)wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數(shù)據(jù)wire full; //FIFO滿信號(hào) wire Empty; //FIFO空信號(hào) wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產(chǎn)生FIFO寫入的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(Empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產(chǎn)生FIFO讀的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(Empty == 1'b1)
標(biāo)簽： fpga fifo verilog quartus
上傳時(shí)間： 2021-12-19
上傳用戶：20125101110
一、建立基本的項(xiàng)目平臺(tái)在建項(xiàng)目平臺(tái)前需要做一些準(zhǔn)備，選擇一個(gè)盤建立 Platform”文件夾，在Platform"文件夾下建boot".HardWareTest"、"Project"、"Src"四個(gè)文件夾，boot"用來(lái)存放bootloader工程程序，HardWareTest"用來(lái)存放硬件自動(dòng)測(cè)試工程程序，"Project"用來(lái)存放項(xiàng)目平臺(tái)建立時(shí)生產(chǎn)的文件，"Src"用來(lái)存放STM32uCOSl工程的應(yīng)用程序。下面開始建項(xiàng)目平臺(tái)吧。步驟一：新建一個(gè) IAR for ARM工程，F(xiàn)ile-> New-> Workspac創(chuàng)建一個(gè)新的工作空間，然后通過(guò)Project >Create New Project建立一個(gè)ARM的Empty project，點(diǎn)擊“OK"后彈出工程保存菜單，填寫工程名“STM32uCOSI"，然后點(diǎn)擊“保存”，第一個(gè)工程建立完畢。步驟二：再建一個(gè)工程，通過(guò)Project > Create New Project建立一個(gè)ARM的Empty project，點(diǎn)擊“OK"后彈出工程保存菜單，填寫工程名“BOOT"，然后點(diǎn)擊“保存”，第二個(gè)工程建立完畢。步驟三：建第三個(gè)工程，通過(guò)Project →> Create New Project建立一個(gè)ARM的Empty project，點(diǎn)擊“OK"后彈出工程保存菜單，填寫工程名“HardWareTest"，然后點(diǎn)擊“保存"，第三個(gè)工程建立完畢。
上傳時(shí)間： 2022-06-26
上傳用戶：
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