Ezusb (cypress) USB 2.0 family firmware for data transfer including 4 ENDPOINTs configuration and crc check
標簽： configuration ENDPOINTs including firmware
上傳時間： 2013-12-18
上傳用戶：愛死愛死
The first task at hand is to set up the ENDPOINTs appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
標簽： appropriately The ENDPOINTs following
上傳時間： 2013-12-02
上傳用戶：dianxin61
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the ENDPOINTs (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標簽： Converters Defini DAC
上傳時間： 2013-10-30
上傳用戶：stvnash
/* * EULER S ALGORITHM 5.1 * * TO APPROXIMATE THE SOLUTION OF THE INITIAL VALUE PROBLEM: * Y = F(T,Y), A<=T<=B, Y(A) = ALPHA, * AT N+1 EQUALLY SPACED POINTS IN THE INTERVAL [A,B]. * * INPUT: ENDPOINTs A,B INITIAL CONDITION ALPHA INTEGER N. * * OUTPUT: APPROXIMATION W TO Y AT THE (N+1) VALUES OF T. */
標簽： APPROXIMATE ALGORITHM THE SOLUTION
上傳時間： 2015-08-20
上傳用戶：zhangliming420
In this application note we will only refer to the FX1. The same terminologies and concept is also used in the FX2. The FX2 has identical FIFO architecture and the same number of ENDPOINTs as the FX1
標簽： terminologies application concept refer
上傳時間： 2014-01-10
上傳用戶：zhangliming420
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four ENDPOINTs, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
標簽： speed USBHostSlave and Supports
上傳時間： 2014-01-17
上傳用戶：sxdtlqqjl
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