Connector/Net 5.0.6 Release Notes --- --- --- Welcome to the release notes for Connector/Net 5.0.6. Important Changes --------------------- There are no major changes in this version. Please see the changelog for the list of bugs fixed.
標(biāo)簽： Connector Net Release Welcome
上傳時(shí)間： 2013-12-16
上傳用戶：zyt
mysql 5.1的 jdbc驅(qū)動(dòng) Connector/J 5.1 支持Mysql 4.1、Mysql 5.0、Mysql 5.1、Mysql 6.0 alpha這些版本。 Connector/J 5.0 支持MySQL 4.1、MySQL 5.0 servers、distributed transaction (XA)。 Connector/J 3.1 支持MySQL 4.1、MySQL 5.0 servers、MySQL 5.0 except distributed transaction (XA) support。 Connector/J 3.0 支持MySQL 3.x or MySQL 4.1。
標(biāo)簽： Mysql Connector 5.1 mysql
上傳時(shí)間： 2014-01-03
上傳用戶：GHF
Java Serial Connector
標(biāo)簽： Connector Serial Java
上傳時(shí)間： 2013-12-20
上傳用戶：love1314
Connector to maxdsl accounts
標(biāo)簽： Connector accounts maxdsl to
上傳時(shí)間： 2017-06-20
上傳用戶：BOBOniu
connector DWGconnector DWGconnector DWGconnector DWGconnector DWG
標(biāo)簽： DWGconnector connector DWG
上傳時(shí)間： 2017-06-24
上傳用戶：894898248
Printer interface with 89c51 controller (LPT Port connector)
標(biāo)簽： controller interface connector Printer
上傳時(shí)間： 2017-08-12
上傳用戶：xjz632
ANSI-VITA 46.7 Ethernet on VPX Fabric Connector
標(biāo)簽： ANSI-VITA
上傳時(shí)間： 2022-06-26
上傳用戶：bluedrops
確保產(chǎn)品之制造性, R&D在設(shè)計(jì)階段必須遵循Layout相關(guān)規(guī)范, 以利制造單位能順利生產(chǎn), 確保產(chǎn)品良率, 降低因設(shè)計(jì)而重工之浪費(fèi). “PCB Layout Rule” Rev1.60 (發(fā)文字號(hào)： MT-8-2-0029)發(fā)文后, 尚有訂定不足之處, 經(jīng)補(bǔ)充修正成“PCB Layout Rule” Rev1.70. PCB Layout Rule Rev1.70, 規(guī)范內(nèi)容如附件所示, 其中分為: (1) ”PCB LAYOUT 基本規(guī)范”:為R&D Layout時(shí)必須遵守的事項(xiàng), 否則SMT,DIP,裁板時(shí)無(wú)法生產(chǎn). (2) “錫偷LAYOUT RULE建議規(guī)范”: 加適合的錫偷可降低短路及錫球. (3) “PCB LAYOUT 建議規(guī)范”:為制造單位為提高量產(chǎn)良率,建議R&D在design階段即加入PCB Layout. (4) ”零件選用建議規(guī)范”: Connector零件在未來(lái)應(yīng)用逐漸廣泛, 又是SMT生產(chǎn)時(shí)是偏移及置件不良的主因,故制造希望R&D及采購(gòu)在購(gòu)買異形零件時(shí)能顧慮制造的需求, 提高自動(dòng)置件的比例. (5) “零件包裝建議規(guī)范”:,零件taping包裝時(shí), taping的公差尺寸規(guī)范,以降低拋料率.
標(biāo)簽： PCB 華碩 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-04-24
上傳用戶：vendy
PCB Layout Rule Rev1.70, 規(guī)範(fàn)內(nèi)容如附件所示, 其中分為: (1) ”PCB LAYOUT 基本規(guī)範(fàn)”:為R&D Layout時(shí)必須遵守的事項(xiàng), 否則SMT,DIP,裁板時(shí)無(wú)法生產(chǎn). (2) “錫偷LAYOUT RULE建議規(guī)範(fàn)”: 加適合的錫偷可降低短路及錫球. (3) “PCB LAYOUT 建議規(guī)範(fàn)”:為製造單位為提高量產(chǎn)良率,建議R&D在design階段即加入PCB Layout. (4) ”零件選用建議規(guī)範(fàn)”: Connector零件在未來(lái)應(yīng)用逐漸廣泛, 又是SMT生產(chǎn)時(shí)是偏移及置件不良的主因,故製造希望R&D及採(cǎi)購(gòu)在購(gòu)買異形零件時(shí)能顧慮製造的需求, 提高自動(dòng)置件的比例.
標(biāo)簽： LAYOUT PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-28
上傳用戶：zhtzht
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
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