12864液晶顯示
標(biāo)簽： 12864 characters pictures DISPLAY
上傳時(shí)間： 2013-11-12
上傳用戶(hù)：懶龍1988
軟件介紹與下載事項(xiàng)： .Zah287 { DISPLAY:none; } _)(^$RFSW#$%T
上傳時(shí)間： 2013-10-28
上傳用戶(hù)：fnggknj
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, DISPLAY, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2013-11-11
上傳用戶(hù)：zwei41
According to CIBC World Markets, Equity Research, theFlat Panel DISPLAY (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward
上傳時(shí)間： 2015-01-02
上傳用戶(hù)：小楓殘?jiān)?/p>
Consumer DISPLAY applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2013-11-01
上傳用戶(hù)：hjkhjk
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen DISPLAY (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video DISPLAY interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：shen_dafa
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, DISPLAY, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2014-12-05
上傳用戶(hù)：qazxsw
§1、安裝： SPB15.2 CD1～3，安裝1、2，第3為庫(kù)，不安裝 License安裝： 設(shè)置環(huán)境變量lm_license_file D:\Cadence\license.dat 修改license中SERVER yyh ANY 5280為SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)設(shè)計(jì)原理圖 進(jìn)入Design Entry CIS Studio 設(shè)置操作環(huán)境\Options\Preferencses: 顏色：colors/Print 格子：Grid DISPLAY 雜項(xiàng)：Miscellaneous .........常取默認(rèn)值
上傳時(shí)間： 2014-01-25
上傳用戶(hù)：wangcehnglin
本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過(guò)Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過(guò)下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中。 關(guān)鍵詞：Verilog HDL；硬件描述語(yǔ)言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock DISPLAY by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
標(biāo)簽： Verilog HDL 多功能 數(shù)字
上傳時(shí)間： 2013-11-10
上傳用戶(hù)：hz07104032
DISPLAYing a large bitmap file on a dialog box, in its original size, is quite difficult in the VC++ environment. However, it is possible to DISPLAY a large bitmap to a predefined area of the dialog by using the StretchBlt( ) function.The major disadvantage of this is that the clarity of the image will be lost. Check out this article for DISPLAYing large bitmaps into the desired area of your dialog box in its original size with a scrolling technique used to show the entire bitmap. 滾動(dòng)顯示位圖 在VC++環(huán)境下，在一個(gè)對(duì)話(huà)框中顯示一個(gè)原始尺寸的大小的位圖文件相當(dāng)是困難的。然而,通過(guò)使用 StretchBlt()函數(shù)一個(gè)給定的區(qū)域顯示一個(gè)大的位圖是可能的。主要的缺點(diǎn)是圖像將會(huì)失真。看了這篇通過(guò)卷動(dòng)技術(shù)顯示整個(gè)位圖技術(shù)的文章，你將能夠以它的原始尺寸在給定對(duì)話(huà)框的區(qū)域內(nèi)顯示一個(gè)大位圖。 來(lái)源: http://www.codeguru.com/bitmap/ScrollBitmap.html
標(biāo)簽： DISPLAYing difficult original bitmap
上傳時(shí)間： 2014-01-05
上傳用戶(hù)：yiwen213
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