The purpose of this lab is to introduce the concept of FSMs with a DATAPATH, and to
study the usage of more complex test benches. Also, we enforce a rudimentary design
methodology by assuming that the students are part of a bigger project, and have no
knowledge of VHDL-implementation of the DATAPATH (made by a hypothetical other
group) other than its predefined Entity Interface until they come to the lab.
The rest of this document is structured as follows: Section 2 describes some prelimi-
nary reading and exercises that should be done before the lab. Section 3 details the
design tasks that should be carried out to pass this lab.
This is a simple MIPS processor DATAPATH written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
