1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時(shí)間： 2022-01-09
上傳用戶：
一個(gè)學(xué)電子工程必備書籍，書里面介紹的很全，適用于出國(guó)黨，而且做科研有一些資料可以參考
標(biāo)簽： 電子工程 晶體管 半導(dǎo)體 電路
上傳時(shí)間： 2022-02-09
上傳用戶：
The PW4554 is a cost-effective, fully integrated high input voltage single-cell Li-ion battery charger.The charger uses a CC/CV charge profile required by Li-ion battery. The charger accepts an inputvoltage up to 24V but is disabled when the input voltage exceeds the OVP threshold, typically 6.8V,to prevent excessive power dissipation. The 24V rating eliminates the over-voltage protection circuitrequired in a low input voltage charger
標(biāo)簽： pw4554
上傳時(shí)間： 2022-02-11
上傳用戶：
PW4203 is a 4.5-22V input, 2A multi-cell synchronous Buck Li-Ion battery charger, suitable forportable application. Select pin is convenient for multi-cell charging. 800 kHz synchronous buckregulator integrates of 22V rating FETs with ultra low on- resistance to achieve high efficiency andsimple circuit design.The PW4203 is available in an 8-pin SOP package, provides a very compact system solution andgood thermal conductance
標(biāo)簽： pw4203
上傳時(shí)間： 2022-02-11
上傳用戶：
The PW2606B is a front-end over voltage and over current protection device. It achieves wide inputvoltage range from 2.5VDC to 40VDC. The over voltage threshold can be programmed externally orset to internal default setting. The low resistance of integrated power path nFET switch ensures betterperformance for battery charging system applications. It can deliver up to 1A current to satisfy thebattery supply system. It integrates the over-temperature protection shutdown and auto-recoverycircuit with hysteresis to protect against over current events
標(biāo)簽： pw2606b
上傳時(shí)間： 2022-02-11
上傳用戶：
The PW2601 is a charger front-end integrated circuit designed to provide protection to Li-ionbatteries from failures of charging circuitry. The device monitors the input voltage, battery voltageand the charging current to make sure all three parameters are operated in normal range. Thedevice will switch off internal MOSFET to disconnect IN to OUT to protect load when any of inputvoltage, output current exceeds the threshold. The Over temperature protection (OTP) functionmonitors chip temperature to protect the device. The PW2601 also can protect the system’sbattery from being over charged by monitors the battery voltage continuously. The deviceoperates like a linear regulator, maintaining a 5.1V output with input voltages up to the input overvoltage threshold.The PW2601 is available in DFN-2x2-8L package. Standard products are Pb-free and Halogenfree
標(biāo)簽： pw2601
上傳時(shí)間： 2022-02-11
上傳用戶：
The PW2202 is silicon N-channel Enhanced VDMOSFETs, is obtained by the self-aligned planarTechnology which reduce the conduction loss, improve switching performance and enhance theavalanche energy. The transistor can be used in various power switching circuit for system
標(biāo)簽： pw2202
上傳時(shí)間： 2022-02-11
上傳用戶：默默
Agilent 34401A Service Guide.pdfIEC Measurement Category II includes electrical devices connected to mains at an outlet on a branch circuit. Such devices include most small appliances, test equipment, and other devices that plug into a branch outlet or socket. The 34401A may be used to make measurements with the HI and LO inputs connected to mains in such devices, or to the branch outlet itself (up to 300 VAC). However, the 34401A may not be used with its HI and LO inputs connected to mains in permanently installed electrical devices such as the main circuit-breaker panel, sub-panel disconnect boxes, or permanently wired motors. Such devices and circuits are subject to overvoltages that may exceed the protection limits of the 34401A. Note: Voltages above 300 VAC may be measured only in circuits that are isolated from mains. However, transient overvoltages are also present on circuits that are isolated from mains. The Agilent 34401A are designed to safely withstand occasional transient overvoltages up to 2500 Vpk. Do not use this equipment to measure circuits where transient overvoltages could exceed this level. Additional Notices Waste Electrical and Electronic Equipment (WEEE) Directive 2002/96/EC This product complies with the WEEE Directive (2002/96/EC) marking requirement. The affixed product label (see below) indicates that you must not discard this electrical/electronic product in domestic household waste. Product Category: With reference to the equipment types in the WEEE directive Annex 1, this product is classified as a "Monitoring and Control instrumentation" product. Do not dispose in domestic household waste. To return unwanted products, contact your local Agilent office, or see www.agilent.com/environment/product for more information. Agilent 34138A Test Lead Set The Agilent 34401A is compatible with the Agilent 34138A Test Lead Set described below. Test Lead Ratings Test Leads - 1000V, 15A Fine Tip Probe Attachments - 300V, 3A Mini Grabber Attachment - 300V, 3A SMT Grabber Attachments - 300V, 3A Operation The Fine Tip, Mini Grabber, and SMT Grabber attachments plug onto the probe end of the Test Leads. Maintenance If any portion of the Test Lead Set is worn or damaged, do not use. Replace with a new Agilent 3413
標(biāo)簽： agilent
上傳時(shí)間： 2022-02-20
上傳用戶：
本書的核心內(nèi)容是關(guān)于半導(dǎo)體器件和有源電路的模擬電子電路基礎(chǔ)。兩位作者Robert L．Boylestad和Louis Nashelsky都是在大學(xué)從事電路分析、電子電路基礎(chǔ)等相關(guān)學(xué)科教學(xué)的資深教授，在電子電路學(xué)科領(lǐng)域出版了多部?jī)?yōu)秀教材，受到很高的評(píng)價(jià)。本書自1972年首次出版至今已經(jīng)修訂至第九版，涵蓋了更廣泛和新穎的內(nèi)容，成為流行30多年的優(yōu)秀經(jīng)典教材。這本改編版在第九版原版內(nèi)容的基礎(chǔ)上，結(jié)合國(guó)內(nèi)高等教育中模擬電子電路課程的特點(diǎn)，進(jìn)行了部分內(nèi)容的調(diào)整。 內(nèi)容提要 本書是英文原版教材Electronic Devices and Circuit Theory,Ninth．Edition之英文改編版《模擬電子技術(shù)》的翻譯版，內(nèi)容包括半導(dǎo)體器件基礎(chǔ)、二極管及其應(yīng)用電路、晶體管和場(chǎng)效應(yīng)管放大電路的基本原理及頻率響應(yīng)、功率放大電路、多級(jí)放大電路、差分放大電路、電流源等模擬集成電路的單元電路、反饋電路、模擬集成運(yùn)算放大器、電壓比較器和波形變換電路等。本書對(duì)原版教材進(jìn)行了改編，精簡(jiǎn)了內(nèi)容，突出了重點(diǎn)，補(bǔ)充了必要知識(shí)點(diǎn)，內(nèi)容更加新穎和系統(tǒng)化，反映了器件和應(yīng)用的發(fā)展趨勢(shì)，強(qiáng)調(diào)了系統(tǒng)工程的概念。 本書與英文版教材配套使用，適合電子、計(jì)算機(jī)、通信等相關(guān)專業(yè)電子電路基礎(chǔ)課程40學(xué)時(shí)到68學(xué)時(shí)的中文或雙語(yǔ)教學(xué)要求，也可供相關(guān)專業(yè)工程技術(shù)人員的學(xué)習(xí)和參考。
標(biāo)簽： 模擬電子
上傳時(shí)間： 2022-03-21
上傳用戶：
電子書-RTL Design Style Guide for Verilog HDL540頁(yè)A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標(biāo)簽： RTL verilog hdl
上傳時(shí)間： 2022-03-21
上傳用戶：canderile
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