快快樂樂學(xué)IC design系列《CELL-Based Design》，芯片設(shè)計(jì)方面的
標(biāo)簽： CELL-Based design Design
上傳時(shí)間： 2013-12-12
上傳用戶：zhichenglu
Synplify Pro是一個(gè)高級(jí)綜合工具。其高級(jí)綜合能力可以使你看到HDL代碼在各種器件（FPGA/Structed ASIC/CELL-Based ASIC）上實(shí)現(xiàn)結(jié)果而無須對(duì)代碼作任何修改。從而選擇最合適的方式來實(shí)現(xiàn)它，或選擇最合適的供應(yīng)商。最主要的功能還是FPGA綜合。
上傳時(shí)間： 2013-04-24
上傳用戶：erkuizhang
Synplify Pro是一個(gè)高級(jí)綜合工具。其高級(jí)綜合能力可以使你看到HDL代碼在各種器件（FPGA/Structed ASIC/CELL-Based ASIC）上實(shí)現(xiàn)結(jié)果而無須對(duì)代碼作任何修改。從而選擇最合適的方式來實(shí)現(xiàn)它，或選擇最合適的供應(yīng)商。最主要的功能還是FPGA綜合。
上傳時(shí)間： 2013-05-15
上傳用戶：eeworm
We introduce a sub-cell WENO reconstruction method to evaluate spatial derivatives in the high-order ADER scheme. The basic idea in our reconstruction is to use only r stencils to reconstruct the point-wise values of solutions and spatial derivatives for the 2r-1 th order ADER scheme in one dimension, while in two dimensions, the dimension-by-dimension sub-cell reconstruction approach for spatial derivatives is employed. Compared with the original ADER scheme of Toro and Titarev (2002) [2] that uses the direct derivatives of reconstructed polynomials for solutions to evaluate spatial derivatives, our method not only reduces greatly the computational costs of the ADER scheme on a given mesh, but also avoids possible numerical oscillations near discontinuities, as demonstrated by a number of one- and two-dimensional numerical tests. All these tests show that the 5th-order ADER scheme based on our sub-cell reconstruction method achieves the desired accuracy, and is essentially non-oscillatory and computationally cheaper for problems with discontinuities.
標(biāo)簽： 高精度格式
上傳時(shí)間： 2016-01-13
上傳用戶：ccsdcczd
資料->【E】光盤論文->【E1】斯坦福博士論文->02 calgary PhD A Java-Based Wireless Framework for Location-Based Services Applications.pdf
標(biāo)簽： Location-Based Applications Java-Based Framework
上傳時(shí)間： 2013-07-02
上傳用戶：亞亞娟娟123
FPGA-based high-order FIR filter design
標(biāo)簽： FPGA-based high-order filter design
上傳時(shí)間： 2013-08-06
上傳用戶：sssnaxie
Digital Down Converter Design based on FPGA.
標(biāo)簽： Converter Digital Design based
上傳時(shí)間： 2013-08-13
上傳用戶：CSUSheep
fpga based jpge 壓縮算法，性能不錯(cuò)，
標(biāo)簽： based fpga jpge 壓縮算法
上傳時(shí)間： 2013-08-14
上傳用戶：a471778
FPGA-based link layer chip S19202 configuration
標(biāo)簽： configuration FPGA-based S19202 layer
上傳時(shí)間： 2013-08-18
上傳用戶：xsnjzljj
Run Pac-man Game Based on 8086/8088 FPGA IP Core
標(biāo)簽： Pac-man Based Game 8086
上傳時(shí)間： 2013-08-23
上傳用戶：JamesB
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