This packet is a IS-95 BasebAnd simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.
標(biāo)簽： simulation BasebAnd channel packet
上傳時間： 2014-11-09
上傳用戶：hwl453472107
his packet is a IS-95 BasebAnd simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.
標(biāo)簽： simulation BasebAnd channel packet
上傳時間： 2013-12-23
上傳用戶：zhangyigenius
Design, Implementation and Testing of a Digital BasebAnd Receiver for Spread Spectrum Telesensing (VHDL)
標(biāo)簽： Implementation Telesensing BasebAnd Receiver
上傳時間： 2015-09-21
上傳用戶：英雄
Simulation of digital BasebAnd modulation,it is very good for the users to deepen their understanding
標(biāo)簽： understandin Simulation modulation BasebAnd
上傳時間： 2014-01-13
上傳用戶：daoxiang126
This packet is a IS-95 BasebAnd simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
標(biāo)簽： simulation BasebAnd channel packet
上傳時間： 2014-12-20
上傳用戶：ukuk
BasebAnd基帶調(diào)制編碼，還有vhdl硬件實現(xiàn)，matlab仿真
標(biāo)簽： BasebAnd 基帶 調(diào)制編碼
上傳時間： 2014-01-15
上傳用戶：ljmwh2000
BasebAnd解調(diào)，vhdl硬件實現(xiàn)，matlab仿真
上傳時間： 2016-05-18
上傳用戶：qq1604324866
This a very simple BasebAnd simulator for SC-FDMA system. This simulator is part of the upcoming book “Single Carrier FDMA: A New Air Interface for Long Term Evolution” (Wiley, Nov. 2008) which I co-authored with professor David J. Goodman at Polytechnic University. The purpose of this simulator is to give some concrete idea of how SC-FDMA system works. It does lack many realistic and sophisticated features such as channel coding, time-varying fading channel model, soft decision decoding, etc. Regardless, I am hoping that it will help you understand SC-FDMA which is a fairly new development in 3GPP LTE.
標(biāo)簽： simulator This BasebAnd upcoming
上傳時間： 2016-08-26
上傳用戶：小草123
A highly optimized DSP architecture for WCDMA BasebAnd processing.pdf
標(biāo)簽： architecture processing optimized BasebAnd
上傳時間： 2016-11-03
上傳用戶：dbs012280
In modern design of digital sysytem,FPGAis widely used,particularly in processing BasebAnd and controlling whole system.The core of this system is based on FPGA.
標(biāo)簽： particularly processing BasebAnd digital
上傳時間： 2016-12-16
上傳用戶：戀天使569
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