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BIt-Plane-Decomposition

vhdl source code for 8 bit datapath logic

vhdl source code for 8 bit datapath logic

標(biāo)簽： datapath source logic vhdl

上傳時(shí)間： 2013-12-15

上傳用戶：開懷常笑
Samsung 8-bit machine the realization of the definition and operation of the sample file spaces

Samsung 8-bit machine the realization of the definition and operation of the sample file spaces

標(biāo)簽： the realization definition operation

上傳時(shí)間： 2013-11-29

上傳用戶：aeiouetla
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.

標(biāo)簽： Wishbone Supports includes Low-Pin

上傳時(shí)間： 2014-12-20

上傳用戶：古谷仁美
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit -

Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added

標(biāo)簽： Consecutive Description AES Features

上傳時(shí)間： 2017-06-25

上傳用戶：talenthn
VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in li

VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.

標(biāo)簽： implementation twofish cipher VHDL

上傳時(shí)間： 2017-06-25

上傳用戶：王小奇
FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flo

FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs

標(biāo)簽： 8226 Testbench FEATURES training

上傳時(shí)間： 2014-01-18

上傳用戶：netwolf
Program for ADC0808 with 4 bit LCD routine. It also includes Protus Debug file.

Program for ADC0808 with 4 bit LCD routine. It also includes Protus Debug file.

標(biāo)簽： includes Program routine Protus

上傳時(shí)間： 2017-06-26

上傳用戶：lili123
COUPLING OF TRANSIENT ELECTROMAGNETIC FIELD TO UNSHIELDED CABLE (over a ground plane)

COUPLING OF TRANSIENT ELECTROMAGNETIC FIELD TO UNSHIELDED CABLE (over a ground plane)

標(biāo)簽： ELECTROMAGNETIC UNSHIELDED TRANSIENT COUPLING

上傳時(shí)間： 2013-12-19

上傳用戶：lingzhichao
verilog code for 3 bit sequence detector

verilog code for 3 bit sequence detector

標(biāo)簽： detector sequence verilog code

上傳時(shí)間： 2017-06-26

上傳用戶：gdgzhym
Bit error rate for QAM in MatLab

Bit error rate for QAM in MatLab

標(biāo)簽： MatLab error rate Bit

上傳時(shí)間： 2017-06-30

上傳用戶：windwolf2000

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