This thesis is devoted to several efficient VLSI ArchITecture design issues in errorcorrecting
coding, including finite field arithmetic, (Generalized) Low-Density Parity-
Check (LDPC) codes, and Reed-Solomon codes.
標簽:
errorcorrecting
ArchITecture
efficient
devoted
上傳時間:
2017-05-08
上傳用戶:康郎