各種功能的計數器實例（VHDL源代碼）:ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;
enable : IN BIT;
up_down : IN BIT;
qa : OUT INTEGER RANGE 0 TO 255;
qb : OUT INTEGER RANGE 0 TO 255;
qc : OUT INTEGER RANGE 0 TO 255;
qd : OUT INTEGER RANGE 0 TO 255;
qe : OUT INTEGER RANGE 0 TO 255;
qf : OUT INTEGER RANGE 0 TO 255;
qg : OUT INTEGER RANGE 0 TO 255;
qh : OUT INTEGER RANGE 0 TO 255;
qi : OUT INTEGER RANGE 0 TO 255;
各種功能的計數器實例（VHDL源代碼）:ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;
enable : IN BIT;
up_down : IN BIT;
qa : OUT INTEGER RANGE 0 TO 255;
qb : OUT INTEGER RANGE 0 TO 255;
qc : OUT INTEGER RANGE 0 TO 255;
qd : OUT INTEGER RANGE 0 TO 255;
qe : OUT INTEGER RANGE 0 TO 255;
qf : OUT INTEGER RANGE 0 TO 255;
qg : OUT INTEGER RANGE 0 TO 255;
qh : OUT INTEGER RANGE 0 TO 255;
qi : OUT INTEGER RANGE 0 TO 255;
