關于FPGA流水線設計的論文 This work investigates the use of very deep Pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing Pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
Efficient Asynchronous Bundled-data Pipelines for DCT Matrix-Vector Multiplication
標簽： Multiplication Matrix-Vector Asynchronous Bundled-data
上傳時間： 2017-09-19
上傳用戶：cuiyashuo
關于FPGA流水線設計的論文\r\nThis work investigates the use of very deep Pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
上傳時間： 2013-09-03
上傳用戶：wl9454
These Simulink blocks contain transfer functions that model the pressure and flow transients for axisymmetric 2D viscous flow of a compressible fluid in a straight rigid circular cross section Pipelines. Three models are available: (1) pressures at the ends (2) flow rates at the ends (3) pressure at one end and flow rate at the other Filtering is incorporated to reduce numerical oscillation (Gibbs phenomenon). See J. Dyn. Systems, Meas. & Control vol 122 (2000) pp. 153-162.
標簽： transients functions Simulink transfer
上傳時間： 2014-01-22
上傳用戶：Shaikh
For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while efficiently managing data flow through the parallel Pipelines of these processes.
標簽： floating-point implementation developers functions
上傳時間： 2013-12-16
上傳用戶：tonyshao
代碼目錄結構：debiandocdriversexamplesincludeobjdictgensrctest.hg_archival.txt.hgignore.hgtags.travis.ymlappveyor.ymlAUTHORSbitbucket-Pipelines.ymlCanFestival-3.vc9.slnCanFestival-3.vc9.vcprojCanFestival-3.vc10.slnCanFestival-3.vc10.vcxprojCanFestival-3.vc10.vcxproj.filtersCanFestival-3.vc15.slnCanFestival-3.vc15.vcxprojconfigureCONTRIBUTORSCOPYINGLICENCEMakefile.inREADME.md
標簽： canopen 源代碼 canfestival
上傳時間： 2022-08-10
上傳用戶：
