16信道0_35_mCMOS_VCSEL光發(fā)射模塊_英文_ 英文 資料
標簽： mCMOS_VCSEL 35 信道 光發(fā)射模塊
上傳時間： 2013-10-26
上傳用戶：lanhuaying
01-接入分冊• 01-ATM和DSL接口配置• 02-CPOS接口配置• 03-POS接口配置• 04-以太網(wǎng)接口配置• 05-WAN接口配置• 06-ATM配置• 07-DCC配置• 08-DLSW配置• 09-幀中繼配置• 10-GVRP配置• 11-HDLC配置• 12-LAPB和X.25 配置• 13-鏈路聚合配置• 14-MODEM配置• 15-端口鏡像配置• 16-PPP配置• 17-網(wǎng)橋配置• 18-ISDN配置• 19-MSTP配置• 20-VLAN配置• 21-端口隔離配置• 22-動態(tài)路由備份配置• 23-邏輯接口配置
上傳時間： 2013-11-25
上傳用戶：europa_lin
ADXL346是一款小而薄的超低功耗3軸加速度計，分辨率高(13位)，測量范圍達±16 g。數(shù)字輸出數(shù)據(jù)為16位二進制補碼格式，可通過SPI(3線或4線)或I2C®數(shù)字接口訪問。
標簽： ADXL 346 超低功耗 數(shù)字加速度計
上傳時間： 2013-11-15
上傳用戶：二十八號
芯嵌stm32開發(fā)板教程
上傳時間： 2013-10-19
上傳用戶：Divine
基于FPGA的16位數(shù)據(jù)路徑的AESIP核
標簽： AESIP FPGA 數(shù)據(jù)路徑
上傳時間： 2013-11-12
上傳用戶：zhangjinzj
飛凌嵌入式7寸屏 原理圖
上傳時間： 2014-12-30
上傳用戶：tecman
文章對美國升級臺灣F-16機載多功能雷達的技術進行了研究。首先介紹了有源電掃相控陣技術，該技術是提高雷達性能的關鍵所在。其次對多普勒銳化和合成孔徑技術進行了深入的討論，研究表明合成孔徑技術能更好地提高成像效果。最后分析了升級F-16帶來的不足，說明升級不能阻止國家的統(tǒng)一大業(yè)。
上傳時間： 2013-11-14
上傳用戶：古谷仁美
FPGA與ARM EPI通信，控制16路步進電機和12路DC馬達 VHDL編寫的，，，，，
上傳時間： 2013-10-31
上傳用戶：chaisz
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
Cadence 16.6 和諧方法 Cadence16.6 Allegro
上傳時間： 2013-10-24
上傳用戶：sjb555
