The main MIPS processor of SMP8630 comes with a JTAG interface, allowing:
access to caches and data bus (DRAM) with a bandwidth of about 200kbit/s
examining the processor state whatever the execution mode (monice)
connecting to monice using mdi-server and using a gdb client on the processor to step and break
accurately whatever the execution mode
running semi-hosted applications
fl ash write tool
memory testing (MT command)
real-time traces: has not been built in CPU (Config3_TL=0) and only supported by MajicPLUS probes
(maybe built into emulator?)
This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
ecos RTOS 原理介紹和應用開發The design philosophy of eCos was to augment an open-source RTOS (which meant no
per-unit royalties) with source-level con?guration tools that would enable embedded developers
to scale their RTOS from hundreds of bytes to hundreds of kilobytes without needing to manu-
ally change a line of source code.
The Embedded Configurable Operating System (eCos)start-to-finish guide to eCos solution building. Additional open source tools are included to configure a complete embedded software development environment.
