I designed the digital multi-function human-computer interaction of arc welding inverter power system
標簽： multi-function human-computer interaction designed
上傳時間： 2017-06-24
上傳用戶：wang0123456789
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
標簽： full-hardware compressor algorithm features
上傳時間： 2014-01-14
上傳用戶：Shaikh
This program is designed for a menu ordering system under pocket pc platform .
標簽： designed ordering platform program
上傳時間： 2014-01-10
上傳用戶：D&L37
Matlab implementation of ID3 and NaiveBayes classifier. It also includes example dataset as well.
標簽： implementation NaiveBayes classifier includes
上傳時間： 2017-06-26
上傳用戶：cx111111
avr book goob book u can understand topic very well
標簽： book understand topic goob
上傳時間： 2017-06-27
上傳用戶：GavinNeko
it is designed using asp.net2005 and c#
上傳時間： 2013-12-12
上傳用戶：lps11188
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
it is a website for online education designed using PHP and HTML
標簽： education designed website online
上傳時間： 2017-07-06
上傳用戶：busterman
provided a modified version of this example that is designed to be more user friendly. It is coded in Delphi 7 Enterprise, and no special components are required.
標簽： provided modified designed friendly
上傳時間： 2017-07-10
上傳用戶：xuanchangri
