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Very-high-speed

  • very comprehensive example, windows WDM driver development ex The use of drive technology can s

    very comprehensive example, windows WDM driver development ex The use of drive technology can s Say all ?� � e full speed equipm STM32 DAC DMA TIXINGBO Implement hiding process, make pr dma ddk driver

    標(biāo)簽: comprehensive development technology example

    上傳時(shí)間: 2013-12-22

    上傳用戶:蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)

  • very comprehensive example, windows WDM driver development ex The use of drive technology can s

    very comprehensive example, windows WDM driver development ex The use of drive technology can s Say all � � e full speed equipm STM32 DAC DMA TIXINGBO Implement hiding process, make pr dma ddk driver

    標(biāo)簽: comprehensive development technology example

    上傳時(shí)間: 2013-12-14

    上傳用戶:alan-ee

  • High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. F

    High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.

    標(biāo)簽: technology 2.0 USB designed

    上傳時(shí)間: 2014-01-02

    上傳用戶:二驅(qū)蚊器

  • High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. F

    High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.

    標(biāo)簽: technology 2.0 USB designed

    上傳時(shí)間: 2017-07-05

    上傳用戶:zhoujunzhen

  • DRM023_3-Phase AC Designer Reference Manual

    This reference design describes the design of a 3-phase AC induction vector control drive with position encoder coupled to the motor shaft. It is based on Motorola’s DSP56F805 dedicated motor control device. AC induction motors, which contain a cage, are very popular in variable speed drives. They are simple, rugged, inexpensive and available at all power ratings. Progress in the field of power electronics and microelectronics enables the application of induction motors for high-performance drives, where traditionally only DC motors were applied. Thanks to sophisticated control methods, AC induction drives offer the same control capabilities as high performance four-quadrant DC drives.

    標(biāo)簽: Reference Designer Manual Phase DRM 023 AC

    上傳時(shí)間: 2020-06-10

    上傳用戶:shancjb

  • 03 California PhD High integrity GPS-INS filter for precise relative navigation.pdf

    資料->【E】光盤(pán)論文->【E1】斯坦福博士論文->03 California PhD High integrity GPS-INS filter for precise relative navigation.pdf

    標(biāo)簽: California navigation integrity relative

    上傳時(shí)間: 2013-07-03

    上傳用戶:jiiszha

  • FPGA-based high-order FIR filter design

    FPGA-based high-order FIR filter design

    標(biāo)簽: FPGA-based high-order filter design

    上傳時(shí)間: 2013-08-06

    上傳用戶:sssnaxie

  • 音頻數(shù)模轉(zhuǎn)換器DAC抖動(dòng)的靈敏度分析

    Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.

    標(biāo)簽: DAC 音頻 數(shù)模轉(zhuǎn)換器 抖動(dòng)

    上傳時(shí)間: 2013-10-25

    上傳用戶:banyou

  • MAX17600數(shù)據(jù)資料

     The MAX17600–MAX17605 devices are high-speedMOSFET drivers capable of sinking /sourcing 4A peakcurrents. The devices have various inverting and noninvertingpart options that provide greater flexibility incontrolling the MOSFET. The devices have internal logiccircuitry that prevents shoot-through during output-statchanges. The logic inputs are protected against voltagespikes up to +14V, regardless of VDD voltage. Propagationdelay time is minimized and matched between the dualchannels. The devices have very fast switching time,combined with short propagation delays (12ns typ),making them ideal for high-frequency circuits. Thedevices operate from a +4V to +14V single powersupply and typically consume 1mA of supply current.The MAX17600/MAX17601 have standard TTLinput logic levels, while the MAX17603 /MAX17604/MAX17605 have CMOS-like high-noise margin (HNM)input logic levels. The MAX17600/MAX17603 are dualinverting input drivers, the MAX17601/MAX17604 aredual noninverting input drivers, and the MAX17602 /MAX17605 devices have one noninverting and oneinverting input. These devices are provided with enablepins (ENA, ENB) for better control of driver operation.

    標(biāo)簽: 17600 MAX 數(shù)據(jù)資料

    上傳時(shí)間: 2013-12-20

    上傳用戶:zhangxin

  • MAX16833高電壓,高亮度LED驅(qū)動(dòng)器分部設(shè)計(jì)

    Abstract: This application note details a step-by-step design process for the MAX16833 high-voltagehigh-brightness LED driver. This process can speed up prototyping and increase the chance for firstpass

    標(biāo)簽: 16833 MAX LED 高電壓

    上傳時(shí)間: 2013-10-09

    上傳用戶:tianjinfan

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