This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
摘要：介紹了基于數(shù)字信號(hào)處理(Digital Signal Processor,DSP)的運(yùn)動(dòng)控制器GT-800在貼片機(jī)控制系統(tǒng)中的應(yīng)用。該系統(tǒng)采用以PC機(jī)為上位機(jī)、GT-800運(yùn)動(dòng)控制器為下位機(jī)的硬件結(jié)構(gòu)，上下位機(jī)之間的通訊采用基于ISA總線的雙端口RAM的模式，系統(tǒng)的軟件設(shè)計(jì)采用基于VisualC++6．0的軟件設(shè)計(jì)模式。關(guān)鍵詞：GT-800運(yùn)動(dòng)控制器；貼片機(jī)；運(yùn)動(dòng)控制；機(jī)器視覺
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI).
The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT).
The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset.
If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on.
In this example the system is clocked by the HSE(8MHz).
通過(guò)以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記
Firmware in embedded hardware systems is frequently updated over the Ethernet. For
embedded systems that comprise a discrete microprocessor and the devices it controls, the
firmware is the software image run by the microprocessor. When the embedded system
includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If
the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as
part of the FPGA image—and the software that the Nios II processor runs, in a single remote
configuration session.
面向Eclips的Nios II軟件構(gòu)建工具手冊(cè)
The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the
Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The
Nios II SBT for Eclipse provides a consistent development platform that works for all
Nios II embedded processor systems. You can accomplish all Nios II software
development tasks within Eclipse, including creating, editing, building, running,
debugging, and profiling programs.
Nios II 軟件開發(fā)人員手冊(cè)中的緩存和緊耦合存儲(chǔ)器部分
Nios® II embedded processor cores can contain instruction and data caches. This
chapter discusses cache-related issues that you need to consider to guarantee that
your program executes correctly on the Nios II processor. Fortunately, most software
based on the Nios II hardware abstraction layer (HAL) works correctly without any
special accommodations for caches. However, some software must manage the cache
directly. For code that needs direct control over the cache, the Nios II architecture
provides facilities to perform the following actions:
