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Two-stage

  • Decoding most of the infrared signals can be easily handled by PIC16C5X microcontrollers. This appl

    Decoding most of the infrared signals can be easily handled by PIC16C5X microcontrollers. This application note describes how this decoding may be done. The only mandatory hardware for decoding IR signals is an infrared receiver. The use of two types is described here. Both are modular types used often by the consumer electronics industry. The first type responds to infrared signals modulated at about 40 kHz. The second responds to non-modulated infrared pulses and has a restricted range. The hardware costs of each approach will be less than two dollars.

    標簽: microcontrollers Decoding infrared handled

    上傳時間: 2015-05-24

    上傳用戶:ruan2570406

  • Writing an interactive Java program with a graphical user interface (GUI) running on the Java phone

    Writing an interactive Java program with a graphical user interface (GUI) running on the Java phone emulator bundled with J2ME Wireless Toolkit 2.2 or Sun Java Wireless Toolkit 2.3 Beta Release. The Jave program will provide a tic-tac-toe board for two players to play a typical tic-tac-toe game on a Java mobile phone.

    標簽: Java interactive graphical interface

    上傳時間: 2014-01-22

    上傳用戶:xuanjie

  • Writing an interactive Java program with a graphical user interface (GUI) running on the Java phone

    Writing an interactive Java program with a graphical user interface (GUI) running on the Java phone emulator bundled with J2ME Wireless Toolkit 2.2 or Sun Java Wireless Toolkit 2.3 Beta Release. The Jave program will provide a Gobang board for two players to play a typical Gobang game on a Java mobile phone.

    標簽: Java interactive graphical interface

    上傳時間: 2015-06-05

    上傳用戶:LouieWu

  • The JICQ is the bureau area which JAVA writes according to "Customer s Machine/Server"(C/S) mode mes

    The JICQ is the bureau area which JAVA writes according to "Customer s Machine/Server"(C/S) mode message solid hour correspond by letter tool system, the system adopted the SQL Server2000 of Microsoft company as a backstage database, the system passes a JDBC interview database. The system is divided into the server procedure and customer s procedure two parts, server and customer adoption "Transmission Control Protocol"(TCP), connect a word (Socket) conjunction through a set, the adoption "User Datagram Protocol "(UDP) of the customer s, pass a data report a set to connect a word (DatagramSocket) establishment a conjunction. The system has customer registration, customer to register, increase good friend, delete good friend and send out and receive news etc. function.

    標簽: according Customer Machine Server

    上傳時間: 2014-01-04

    上傳用戶:jyycc

  • Single-layer neural networks can be trained using various learning algorithms. The best-known algori

    Single-layer neural networks can be trained using various learning algorithms. The best-known algorithms are the Adaline, Perceptron and Backpropagation algorithms for supervised learning. The first two are specific to single-layer neural networks while the third can be generalized to multi-layer perceptrons.

    標簽: Single-layer algorithms best-known networks

    上傳時間: 2015-06-17

    上傳用戶:趙云興

  • Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this mo

    Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution % % compute the forward/backward Campbell/specgtrogram % % INPUT: % y (n x 2) each column is measured from a different sensor % /////// % __ % |s1| y(:,1) % |__| % __ % / \ ________|/ % | | | s2 |/ y(:,2) % \____/ --------|/ % % Fs Sampling frequnecy % % OUTPUT: % B spectrogram/Campbel diagram % x x-axis coordinate vector (time or Speed) % y y-axis coordinate vector (frequency [Hz])

    標簽: experience elliptical decompose important

    上傳時間: 2015-06-23

    上傳用戶:372825274

  • 一種基于二維鏈表的稀疏矩陣模半板類設計 A template Class of sparse matrix. Key technology: bin,2-m linked matrix. con

    一種基于二維鏈表的稀疏矩陣模半板類設計 A template Class of sparse matrix. Key technology: bin,2-m linked matrix. constructors: 1.normal constuctor 2.copy constuctor. 3.assignment constructor. Basic operator: 1. addition(sub) of two matrix 2. inverse of a matrix. 3. multiply of two matrix. etc.

    標簽: matrix technology template linked

    上傳時間: 2013-12-13

    上傳用戶:lwwhust

  • 這是06年4月剛剛完成的程序

    這是06年4月剛剛完成的程序,從opencore.org下載而來。用vhdl語言描寫,以及matlab仿真,testbench,以及在xinlinx上的綜合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation.

    標簽: 程序

    上傳時間: 2013-12-16

    上傳用戶:123啊

  • merge sort give a set S of n integers and another integer x, determine whether or not there exits tw

    merge sort give a set S of n integers and another integer x, determine whether or not there exits two elements in S whose sum is exactly x.

    標簽: determine integers another integer

    上傳時間: 2013-12-23

    上傳用戶:xmsmh

  • 關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標簽: investigates implementing pipelines circuits

    上傳時間: 2015-07-26

    上傳用戶:CHINA526

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