The Finite Difference Time Domain Method for Electromagnetics With MATLAB Simulations Atef Elsherbeni and Veysel Demir Chapter 9
標(biāo)簽： Electromagnetics Simulations Difference Finite
上傳時間： 2017-07-05
上傳用戶：cc1
The Finite Difference Time Domain Method for Electromagnetics With MATLAB Simulations Atef Elsherbeni and Veysel Demir Chapter 10
標(biāo)簽： Electromagnetics Simulations Difference Finite
上傳時間： 2017-07-05
上傳用戶：離殤
The Finite Difference Time Domain Method for Electromagnetics With MATLAB Simulations Atef Elsherbeni and Veysel Demir Chapter 11
標(biāo)簽： Electromagnetics Simulations Difference Finite
上傳時間： 2013-12-19
上傳用戶：壞壞的華仔
The Finite Difference Time Domain Method for Electromagnetics With MATLAB Simulations Atef Elsherbeni and Veysel Demir Chapter 12
標(biāo)簽： Electromagnetics Simulations Difference Finite
上傳時間： 2017-07-05
上傳用戶：comua
The Finite Difference Time Domain Method for Electromagnetics With MATLAB Simulations Atef Elsherbeni and Veysel Demir Applendix A
標(biāo)簽： Electromagnetics Simulations Difference Finite
上傳時間： 2014-01-20
上傳用戶：invtnewer
artificial inteligence system to determine high angular frequency in matlab
標(biāo)簽： inteligence artificial determine frequency
上傳時間： 2017-07-05
上傳用戶：youmo81
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
標(biāo)簽： application real-time Synopsys emphasis
上傳時間： 2017-07-05
上傳用戶：waitingfy
one tool used to control the real time logger
標(biāo)簽： control logger tool real
上傳時間： 2017-07-05
上傳用戶：wmwai1314
Linux for Embedded and Real-time Applications
標(biāo)簽： Applications Real-time Embedded Linux
上傳時間： 2017-07-05
上傳用戶：yzy6007
Chip type : ATmega16L Program type : Application Clock frequency : 4.000000 MHz Memory model : Small External SRAM size : 0 Data Stack size : 256
標(biāo)簽： type Application frequency 4.000000
上傳時間： 2014-01-08
上傳用戶：lx9076
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