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SpecificATions

產(chǎn)品規(guī)格(SpecificATions)是指物件的體積、大小、型號(hào)。是用來識(shí)別物品的編號(hào)。中國最早沒有編號(hào)規(guī)則,一汽投產(chǎn)時(shí)是CA10、CA30等參考蘇聯(lián)的編號(hào)。
  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing SpecificATions: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    標(biāo)簽: Transceiver Virtex Wizar GTP

    上傳時(shí)間: 2013-10-20

    上傳用戶:dave520l

  • pci e PCB設(shè)計(jì)規(guī)范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable SpecificATions. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    標(biāo)簽: pci PCB 設(shè)計(jì)規(guī)范

    上傳時(shí)間: 2014-01-24

    上傳用戶:s363994250

  • In today’s IT environment, Java is a leading technology in the world of enterprise development. As

    In today’s IT environment, Java is a leading technology in the world of enterprise development. As management demands more from technology, complexity in infrastructure seems to grow exponentially, leaving many unable to keep up with the demands of such a fast-paced world. These complexities can be seen in the over-evolving Java 2 Enterprise Edition (J2EE) SpecificATions. This unnecessary complexity drove us to discover ways of simplifying development.

    標(biāo)簽: environment development enterprise technology

    上傳時(shí)間: 2013-12-24

    上傳用戶:Zxcvbnm

  • 利用FaxModem通過串口或TAPI接口直接發(fā)送和接收傳真 一套非常不錯(cuò)的傳真庫(穩(wěn)定

    利用FaxModem通過串口或TAPI接口直接發(fā)送和接收傳真 一套非常不錯(cuò)的傳真庫(穩(wěn)定,高速),幾乎支持所有的FaxModem,出自Symantec公司 Winfax 中國作者之手。 一 .Some of the standard features: 1.Comes with Class1, Class1.0, Class2 and Class 2.0 Fax Drivers 2.Class 1 ECM error correction . 3.Supports CCITT T.30 SpecificATions . 4.TAPI Support with sample code 5.Caller ID 6.Group 4 Faxing 7.Remote Fax Retrieval with password protection 二 .Function declare Reference: include\SmarFaxh.h

    標(biāo)簽: FaxModem TAPI 傳真 串口

    上傳時(shí)間: 2013-12-23

    上傳用戶:xiaoyunyun

  • This library provides functionality to control any camera that conforms to the 1394-Based Digital C

    This library provides functionality to control any camera that conforms to the 1394-Based Digital Camera Specification (which can be found at http://www.1394ta.org/Download/Technology/SpecificATions/Camera120.pdf). It utilizes the lowlevel functionality provided by libraw1394 to communicate with the camera.

    標(biāo)簽: functionality conforms provides Digital

    上傳時(shí)間: 2013-12-23

    上傳用戶:yuchunhai1990

  • the applet is used for Grocery Store Simulation,When you execute the main() method, the output shoul

    the applet is used for Grocery Store Simulation,When you execute the main() method, the output should match the output file provided in the course website. You will be graded according to the correctness of your output and your compliance to these SpecificATions.

    標(biāo)簽: the Simulation Grocery execute

    上傳時(shí)間: 2013-12-25

    上傳用戶:luopoguixiong

  • 一個(gè)簡單的SPI IP核

    一個(gè)簡單的SPI IP核,SPI Core SpecificATions 可以從說明文檔中找到! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI SpecificATions · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable

    標(biāo)簽:

    上傳時(shí)間: 2015-09-17

    上傳用戶:TRIFCT

  • CheckMate is a MATLAB-based tool for modeling, simulating and investigating properties of hybrid dyn

    CheckMate is a MATLAB-based tool for modeling, simulating and investigating properties of hybrid dynamic systems. Hybrid systems are modeled using the Simulink graphical user interface (GUI). Parameters and SpecificATions are entered using both the Simulink GUI and user-defined m-files. CheckMate commands are entered in the MATLAB command window.

    標(biāo)簽: investigating MATLAB-based simulating properties

    上傳時(shí)間: 2013-12-13

    上傳用戶:源弋弋

  • Obtain the CDF plots of PAPR from an OFDM BPSK transmission specified per IEEE 802.11a specification

    Obtain the CDF plots of PAPR from an OFDM BPSK transmission specified per IEEE 802.11a specification Per the IEEE 802.11a SpecificATions, we 52 have used subcarriers. Given so, the theoretical maximum expected PAPR is 52 (around 17dB). However, thanks to the scrambler, all the subcarriers in an OFDM symbol being equally modulated is unlikely. Using a small script, the cumulative distribution of PAPR from each OFDM symbol, modulated by a random BPSK signal is obtained

    標(biāo)簽: specification transmission specified Obtain

    上傳時(shí)間: 2016-04-24

    上傳用戶:haoxiyizhong

  • * Explains process algebra and protocol specification using µ CRL, a language developed to combi

    * Explains process algebra and protocol specification using µ CRL, a language developed to combine process algebra and abstract data types * Text is supported throughout with examples and exercises * Full solutions are provided in an appendix, while exercise sheets, lab exercises, example SpecificATions and lecturer slides are available on the author s website

    標(biāo)簽: specification developed Explains language

    上傳時(shí)間: 2016-04-27

    上傳用戶:笨小孩

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