<input id="4kmus"></input> MIG生成的DDR2相關的代碼
上傳時間： 2013-10-12
上傳用戶：z1191176801
基于FPGA、PCI9054、SDRAM和DDS設計了用于某遙測信號模擬源的專用板卡。PCI9054實現與上位機的數據交互,FPGA實現PCI本地接口轉換、數據接收發送控制及DDS芯片的配置。通過WDM驅動程序設計及MFC交互界面設計,最終實現了10~200 Mbit·s-1的LVDS數據接收及10~50 Mbit·s-1任意速率的LVDS數據發送。
上傳時間： 2013-12-24
上傳用戶：zhangchu0807
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
上傳時間： 2013-11-06
上傳用戶：windgate
介紹關于內存的內部結構，與內存知識。主要講解了SDRAM方面
標簽： 內存技術
上傳時間： 2013-11-20
上傳用戶：hehuaiyu
S3C44BOX的BIOS。可使用的命令：help --- show help ? --- = help date --- show or set current date time --- show or set current time setweek --- set weekday clock --- show system running clock setmclk --- set system running clock setbaud ------ set baud rate ipcfg ------ show or set IP address load ------ load file to ram comload ------ load file from serial port run ------ run from sdram prog ------ program flash copy ------ copy flash from src to dst address boot ------ boot from flash backup ------ move bios to the top of flash md ------ show memory data move ------ move program from flash to sdram
上傳時間： 2015-01-22
上傳用戶：ANRAN
杭州利宇泰公司的基于44B0的ARMSys開發板上的大量源代碼，包括ADC、ARP、彩色LCD、外部中斷、以太網底層函數、FAT16文件系統、Flash ROM、GUI軟件包、Helloworld程序、IIC接口、掃描鍵盤、Ping程序、44B0內置RTC示例、SDRAM接口、定時器示例、觸摸屏示例、UART示例和uC/OS-II的移植、應用（包括多任務、任務間通信、中斷服務程序）、UDP數據傳輸、USB固件編寫等程序代碼和工程。一次性共享給大家使用。可以作為其他samsung44B0開發板上應用程序的下載。
上傳時間： 2013-11-30
上傳用戶：小鵬
mcf5307實驗源代碼，包括I2C、flash sdram LED1335液晶屏源代碼
上傳時間： 2013-12-08
上傳用戶：zhanditian
PCI驅動編程實例，通過PCI可實施操作： 2、通過DMA方式往SDRAM寫數據的步驟： (1) 往OMB1寫傳輸數據次數 (2) 往OMB2寫所要訪問的SDRAM地址 (3) 往FIFO寫2 3、通過DMA方式從SDRAM讀數據的步驟： (1) 往OMB1寫傳輸數據次數 (2) 往OMB2寫所要訪問的SDRAM地址 (3) 往FIFO寫3
上傳時間： 2014-01-11
上傳用戶：woshiayin
