ADI實(shí)驗(yàn)室電路時(shí)經(jīng)過(guò)構(gòu)建和測(cè)試可以確保功能和性能的電路設(shè)計(jì) 借助ADI公司了眾多應(yīng)用專業(yè)技術(shù)，解決了多種常見(jiàn)的模擬、RF/IF和混合信號(hào)設(shè)計(jì)挑戰(zhàn)。 所以我覺(jué)得這個(gè)還是非常值得我們學(xué)習(xí)的，特此分享一下
標(biāo)簽： ADI 模塊 實(shí)驗(yàn)室電路 設(shè)計(jì)指南
上傳時(shí)間： 2013-06-20
上傳用戶：manlian
國(guó)產(chǎn)仿三菱PLC源代碼 /* _LD,_LDI,_AND,_ANI,_OR,_ORI,_INV,_OUT(_OUT_T,_OUT_C),_SET,_RST,_ANB,_ORB,_LDP,_LDF,_ANDP,_ANDF, */ /* _ORP,_ORF,_PLS,_PLF,_MPS,_MRD,_MPP,_NOP,END,_ADD,_SUB,_MUL,_DIV,_INC,_DEC,_WAND,_WOR,_WXOR, */ /* _NEG,_ALT,_MOV,_CML,_XCH,_BCD,_BIN,_CMP,_ZCP,_FMOV,_ROR,_ROL,_ZRST,_REF,_ASCI,_SWAP,_CJ,_CALL, */ /* _SRET,_FEND,_LD>=,_LD,_LD=,_AND,_AND=,_OR,_OR
上傳時(shí)間： 2013-07-28
上傳用戶：sssl
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時(shí)間： 2013-11-22
上傳用戶：han_zh
本文介紹了AD公司的RF/IF相位和幅度測(cè)量芯片AD8302，并以此芯片為核心，組合功分器、延遲線和FPGA芯片設(shè)計(jì)了瞬時(shí)測(cè)頻接收機(jī)，改進(jìn)了傳統(tǒng)的設(shè)計(jì)方案。依照設(shè)計(jì)制作了測(cè)頻系統(tǒng)，并對(duì)系統(tǒng)整體性能進(jìn)行了測(cè)試，測(cè)試結(jié)果表明本系統(tǒng)可以準(zhǔn)確測(cè)量1.4~2.0 GHz范圍內(nèi)的信號(hào)，測(cè)頻精度為10 MHz。
標(biāo)簽： 數(shù)字測(cè)頻 接收機(jī)
上傳時(shí)間： 2013-10-26
上傳用戶：zsjzc
Abstract: This application note describes the essential workings of an electrocardiogram (ECG). It discussesfactors that disrupt the ECG signals and make reliable, highly-accurate electrical characterization difficult. Theindustry-standard solution for ECG electrical characterization, which uses an analog front-end and ADCcombination, is explained. The article then introduces the MAX11040 simultaneous-sampling, sigma-deltaADC as a compelling, highly integrated solution that eliminates the need for the AFE, and saves both spaceand cost for the application.
標(biāo)簽： ADC 24位 心電圖 中的應(yīng)用
上傳時(shí)間： 2013-12-23
上傳用戶：sssl
Abstract: This tutorial discusses proper printed-circuit board (PCB) grounding for mixed-signal designs. Formost applications a simple method without cuts in the ground plane allows for successful PCB layouts withthis kind of IC. We begin this document with the basics: where the current flows. Later, we describe how toplace components and route signal traces to minimize problems with crosstalk. Finally, we move on toconsider power supply-currents and end by discussing how to extend what we have learned to circuits withmultiple mixed-signal ICs.
標(biāo)簽： PCB 正 印刷電路板 混合信號(hào)
上傳時(shí)間： 2013-11-04
上傳用戶：pol123
本書(shū)內(nèi)容包括三大部分：第1 部分從運(yùn)算放大器的基本概念和理論出發(fā)，重點(diǎn)介紹了運(yùn)算放大器的原理與設(shè)計(jì)，以及在各種電子系統(tǒng)中的應(yīng)用，包括視頻應(yīng)用、RF/IF 子系統(tǒng)(乘法器、調(diào)制器和混頻器)等;第2 部分主要介紹了高速采樣和高速ADC 及其應(yīng)用、高速DAC 及其應(yīng)用、以及DDS 系統(tǒng)與接收機(jī)子系統(tǒng)等;第3 部分介紹了有關(guān)高速硬件設(shè)計(jì)技術(shù)，如仿真、建模、原型、布局、去藕與接地，以及EMI 與RFI設(shè)計(jì)考慮等。 書(shū)中內(nèi)容既有完整的理論分析，又有具體的實(shí)際應(yīng)用電路，還包括許多應(yīng)用技巧。特別適合電子電路與系統(tǒng)設(shè)計(jì)工程師、高等院校相關(guān)專業(yè)師生閱讀。
標(biāo)簽： ADI 處理器 高速設(shè)計(jì)
上傳時(shí)間： 2013-11-16
上傳用戶：qitiand
Abstract: If sensitive analog systems are run from one supply without the sufficient bypassing to eliminate noise,
上傳時(shí)間： 2013-11-23
上傳用戶：qiulin1010
Precision 16-bit analog outputs with softwareconfigurableoutput ranges are often needed in industrialprocess control equipment, analytical and scientificinstruments and automatic test equipment. In the past,designing a universal output module was a daunting taskand the cost and PCB real estate associated with thisfunction were problematic, if not prohibitive.
上傳時(shí)間： 2014-12-23
上傳用戶：如果你也聽(tīng)說(shuō)
Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.
標(biāo)簽： 數(shù)字接收器 信號(hào)鏈 噪聲分析
上傳時(shí)間： 2014-12-05
上傳用戶：cylnpy
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