微弱信號檢測裝置
四川理工學院 劉鵬飛、梁天德、曾學明
摘要：
本設計以TI的Launch Pad為核心板，采用鎖相放大技術設計并制作了一套微弱信號檢測裝置，用以檢測在強噪聲背景下已知頻率微弱正弦波信號的幅度值，并在液晶屏上數字顯示出所測信號相應的幅度值。實驗結果顯示其抗干擾能力強，測量精度高。
關鍵詞：強噪聲；微弱信號；鎖相放大；Launch Pad
Abstract:
This design is based on the Launch Pad of TI core board, using a lock-in amplifier technique designed and produced a weak signal detection DeviCE, to measure the known frequency sine wave signal amplitude values of the weak in the high noise background, and shows the measured signal amplitude of the corresponding value in the liquid crystal screen. Test results showed that it has high accuracy and strong anti-jamming capability.
Keywords: weak signal detection; lock-in-amplifier; Launch Pad
1、引言
隨著現代科學技術的發展，在科研與生產過程中人們越來越需要從復雜高強度的噪聲中檢測出有用的微弱信號，因此對微弱信號的檢測成為當前科研的熱點。微弱信號并不意味著信號幅度小，而是指被噪聲淹沒的信號，“微弱”也僅是相對于噪聲而言的。只有在有效抑制噪聲的條件下有選擇的放大微弱信號的幅度，才能提取出有用信號。微弱信號檢測技術的應用相當廣泛，在生物醫學、光學、電學、材料科學等相關領域顯得愈發重要。
2、方案論證
針對微弱信號的檢測的方法有很多，比如濾波法、取樣積分器、鎖相放大器等。下面就針對這幾種方法做一簡要說明。
方案一：濾波法。
在大部分的檢測儀器中都要用到濾波方法對模擬信號進行一定的處理，例如隔離直流分量，改善信號波形，防止離散化時的波形混疊，克服噪聲的不利影響，提高信噪比等。常用的噪聲濾波器有：帶通、帶阻、高通、低通等。但是濾波方法檢測信號不能用于信號頻譜與噪聲頻譜重疊的情況，有其局限性。雖然可以對濾波器的通頻帶進行調節，但其噪聲抑制能力有限，同時其準確性與穩定性將大打折扣。
Recently a new technology for high voltage Power MOSFETshas been introduced – the CoolMOS™ . Based on thenew DeviCE concept of charge compensation the RDS(on) areaproduct for e.g. 600V transistors has been reduced by afactor of 5. The DeviCEs show no bipolar current contributionlike the well known tail current observed during the turn-offphase of IGBTs. CoolMOS™ virtually combines the lowswitching losses of a MOSFET with the on-state losses of anIGBT.
Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of DeviCE resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to DeviCE power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof DeviCE frequency.
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the DeviCE) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the DeviCE achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express DeviCEs located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express DeviCE located “down” on the baseboard and a DeviCE located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
