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20v

  • 數(shù)控直流電源.步進(jìn)0.1V可調(diào)節(jié)電壓0到20v,輸出電壓通過(guò)數(shù)碼管顯示,并且有掉電存儲(chǔ)功能

    數(shù)控直流電源.步進(jìn)0.1V可調(diào)節(jié)電壓0到20v,輸出電壓通過(guò)數(shù)碼管顯示,并且有掉電存儲(chǔ)功能

    標(biāo)簽: 0.1 20 數(shù)控直流電源 掉電

    上傳時(shí)間: 2014-11-27

    上傳用戶:3到15

  • 基于單片機(jī)。可實(shí)現(xiàn)2V,20v,200V,2000V的多位選檔功能

    基于單片機(jī)。可實(shí)現(xiàn)2V,20v,200V,2000V的多位選檔功能

    標(biāo)簽: 2000 200 20 單片機(jī)

    上傳時(shí)間: 2014-11-22

    上傳用戶:1109003457

  • 自調(diào)量程數(shù)字電壓表 自動(dòng)實(shí)現(xiàn)200MV檔 2V檔 20v檔的量程調(diào)換

    自調(diào)量程數(shù)字電壓表 自動(dòng)實(shí)現(xiàn)200MV檔 2V檔 20v檔的量程調(diào)換

    標(biāo)簽: 200 20v MV 數(shù)字電壓表

    上傳時(shí)間: 2013-12-03

    上傳用戶:咔樂(lè)塢

  • Atmega8控制LM317的數(shù)控電源0-20v輸出(原理圖+PCB+程序源碼)

    Atmega8控制LM317的數(shù)控電源0-20v輸出(原理圖+PCB+程序源碼)

    標(biāo)簽: lm317 數(shù)控電源 原理圖 pcb

    上傳時(shí)間: 2022-07-28

    上傳用戶:qdxqdxqdxqdx

  • 模擬信號(hào)發(fā)生頻率計(jì)方法

    ? 計(jì)算方法: 1) A值(相位)的計(jì)算:根據(jù)設(shè)置的相位值D(單位為度,0度-360度可設(shè)置),由公式A=D/360,得出A值,按四舍五入的方法得出相位A的最終值; 2) B偏移量值的計(jì)算:按B=512*(1/2VPP-VDC+20)/5; 3) C峰峰值的計(jì)算:按C=VPP/20v*4095;

    標(biāo)簽: 模擬信號(hào) 發(fā)生 頻率計(jì)

    上傳時(shí)間: 2013-11-18

    上傳用戶:xdqm

  • 基于單片機(jī)的數(shù)控電壓源設(shè)計(jì)

    一款0-20v,2A輸出的數(shù)控電壓源,運(yùn)用了并聯(lián)均流輸出的畢業(yè)設(shè)計(jì)。

    標(biāo)簽: 單片機(jī) 數(shù)控電壓源

    上傳時(shí)間: 2013-11-12

    上傳用戶:31633073

  • 反激式控制器簡(jiǎn)化了低輸入電壓DCDC轉(zhuǎn)換器的設(shè)計(jì)

    LT®3837 從一個(gè) 4.5V 至 20v 輸入獲取工作電壓,但可通過(guò)采用一個(gè) VCC 穩(wěn)壓器和 / 或變壓器上的一個(gè)偏壓繞組使該轉(zhuǎn)換器的輸入範(fàn)圍向上擴(kuò)展。

    標(biāo)簽: DCDC 反激式控制器 輸入電壓 轉(zhuǎn)換器

    上傳時(shí)間: 2013-11-01

    上傳用戶:

  • 主板電源接口詳解(圖解)

    計(jì)算機(jī)的ATX電源脫離主板是需要短接一下20芯接頭上的綠色(power on)和黑色(地)才能啟動(dòng)的。啟動(dòng)后把萬(wàn)用表?yè)艿街髁麟妷?b>20v檔位,把黑表筆插入4芯D型插頭的黑色接線孔中,用紅表筆分別測(cè)量各個(gè)端子的電壓。樓上列的是20芯接頭的端子電壓,4芯D型插頭的電壓是黃色+12V,黑色地,紅色+5V。  主板電源接口 圖解 20-PIN ATX主板電源接口

    標(biāo)簽: 主板電源 接口 圖解

    上傳時(shí)間: 2013-10-28

    上傳用戶:蔣清華嗯

  • 直流穩(wěn)壓源的設(shè)計(jì).pdf

    本設(shè)計(jì)采用串聯(lián)型直流穩(wěn)壓源的基本思路進(jìn)行設(shè)計(jì),得到0~20v 的穩(wěn)定直流電壓輸出,電 壓調(diào)整率、負(fù)載調(diào)整率,以及輸出電壓紋波等參數(shù)都達(dá)到較高水平,并具有限流和顯示電壓值、 電流值的功能,且操作方便。

    標(biāo)簽: 直流穩(wěn)壓源

    上傳時(shí)間: 2014-12-24

    上傳用戶:fdmpy

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20v/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標(biāo)簽: Signal Input Fall Rise

    上傳時(shí)間: 2013-10-23

    上傳用戶:copu

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