相 關(guān) 資 源

• fifo pointers in verilog gray code utilization for synchronius免費(fèi)下載

  資源簡(jiǎn)介：fifo pointers in verilog gray code utilization for synchronius

  標(biāo)簽： utilization synchronius pointers verilog

  上傳時(shí)間： 2014-11-24

  上傳用戶：silenthink

• Generic FIFO, writen in verilog hdl免費(fèi)下載

  資源簡(jiǎn)介：Generic FIFO, writen in verilog hdl

  標(biāo)簽： Generic verilog writen FIFO

  上傳時(shí)間： 2016-02-18

  上傳用戶：zwei41

• serial port rs232 in verilog source code免費(fèi)下載

  資源簡(jiǎn)介：serial port rs232 in verilog source code

  標(biāo)簽： verilog serial source port

  上傳時(shí)間： 2014-12-03

  上傳用戶：songyue1991

• it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8免費(fèi)下載

  資源簡(jiǎn)介：it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is requir...

  標(biāo)簽： synthesize simulator modelsim verilog

  上傳時(shí)間： 2014-06-26

  上傳用戶：zhuyibin

• it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x免費(fèi)下載

  資源簡(jiǎn)介：it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

  標(biāo)簽： synthesize simulator modelsim interin

  上傳時(shí)間： 2017-03-22

  上傳用戶：洛木卓

• it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin免費(fèi)下載

  資源簡(jiǎn)介：it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

  標(biāo)簽： synthesize simulator modelsim digital

  上傳時(shí)間： 2014-01-10

  上傳用戶：kernaling

• it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have免費(fèi)下載

  資源簡(jiǎn)介：it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.

  標(biāo)簽： controller synthesize verilog traffic

  上傳時(shí)間： 2017-03-22

  上傳用戶：xymbian

• it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix免費(fèi)下載

  資源簡(jiǎn)介：it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

  標(biāo)簽： synthesize verilog machine written

  上傳時(shí)間： 2013-12-11

  上傳用戶：yepeng139

• this is a code for DDS in verilog免費(fèi)下載

  資源簡(jiǎn)介：this is a code for DDS in verilog

  標(biāo)簽： verilog this code DDS

  上傳時(shí)間： 2013-12-03

  上傳用戶：sdq_123

• code for fpga is written in verilog,cardinality is a thing which is very important免費(fèi)下載

  資源簡(jiǎn)介：code for fpga is written in verilog,cardinality is a thing which is very important

  標(biāo)簽： cardinality important is written

  上傳時(shí)間： 2013-12-20

  上傳用戶：moerwang

• it is source code of 32 bit register and testbench for tht register written in verilog.免費(fèi)下載

  資源簡(jiǎn)介：it is source code of 32 bit register and testbench for tht register written in verilog.

  標(biāo)簽： register testbench written verilog

  上傳時(shí)間： 2014-12-21

  上傳用戶：youmo81

• pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.免費(fèi)下載

  資源簡(jiǎn)介：pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.

  標(biāo)簽： source code the verilog

  上傳時(shí)間： 2014-01-22

  上傳用戶：曹云鵬

• mining source code written in verilog免費(fèi)下載

  資源簡(jiǎn)介：mining source code written in verilog

  標(biāo)簽： verilog written mining source

  上傳時(shí)間： 2015-05-06

  上傳用戶：asddsd

• The source code samples for chapter 2, 4, 6, and 8 are contained in the EvenChapters project. Those免費(fèi)下載

  資源簡(jiǎn)介：The source code samples for chapter 2, 4, 6, and 8 are contained in the EvenChapters project. Those chapters all reference various aspects of this single project. The source code for the BullsEye control (chapter 10 example) is in the B...

  標(biāo)簽： EvenChapters contained chapter samples

  上傳時(shí)間： 2015-09-07

  上傳用戶：yuchunhai1990

• White paper - Comparison of VHDL, verilog and Systemverilog Good for one interetsted in using n of免費(fèi)下載

  資源簡(jiǎn)介：White paper - Comparison of VHDL, verilog and Systemverilog Good for one interetsted in using n of VHDL, verilog and Systemverilog languages

  標(biāo)簽： Systemverilog interetsted Comparison verilog

  上傳時(shí)間： 2013-12-21

  上傳用戶：yulg

• As the source code name, this code is writing in verilog and also inside the folder there is a c cod免費(fèi)下載

  資源簡(jiǎn)介：As the source code name, this code is writing in verilog and also inside the folder there is a c code to see the simulation results from verilog.

  標(biāo)簽： code the verilog writing

  上傳時(shí)間： 2013-12-27

  上傳用戶：wangdean1101

• this code is in Matlab.and this code od for Speaker recognitoin system.免費(fèi)下載

  資源簡(jiǎn)介：this code is in Matlab.and this code od for Speaker recognitoin system.

  標(biāo)簽： this code recognitoin Speaker

  上傳時(shí)間： 2013-12-15

  上傳用戶：aa17807091

• Kalman filter in c c++ code, the five Kalman equations have been implemented for randomly generated免費(fèi)下載

  資源簡(jiǎn)介：Kalman filter in c c++ code, the five Kalman equations have been implemented for randomly generated data.

  標(biāo)簽： Kalman implemented equations generated

  上傳時(shí)間： 2017-04-27

  上傳用戶：lmeeworm

• code source for a chronometer which display in OSD免費(fèi)下載

  資源簡(jiǎn)介：code source for a chronometer which display in OSD

  標(biāo)簽： chronometer display source which

  上傳時(shí)間： 2017-05-07

  上傳用戶：gxmm

• code about gtk++ for MID intel develop in Linux moblin. code interface write as language c in linu免費(fèi)下載

  資源簡(jiǎn)介：code about gtk++ for MID intel develop in Linux moblin. code interface write as language c in linux, compiler is gcc

  標(biāo)簽： code interface language develop

  上傳時(shí)間： 2014-01-08

  上傳用戶：王小奇

• verilog source code for uart design免費(fèi)下載

  資源簡(jiǎn)介：verilog source code for uart design

  標(biāo)簽： verilog source design code

  上傳時(shí)間： 2014-01-11

  上傳用戶：silenthink

• Files in matlab source code for watermarking techniqe免費(fèi)下載

  資源簡(jiǎn)介：Files in matlab source code for watermarking techniqe

  標(biāo)簽： watermarking techniqe matlab source

  上傳時(shí)間： 2014-01-09

  上傳用戶：hxy200501

• Quartus appendix - Can be useful if you start using quartus II to code in verilog免費(fèi)下載

  資源簡(jiǎn)介：Quartus appendix - Can be useful if you start using quartus II to code in verilog

  標(biāo)簽： appendix Quartus quartus verilog

  上傳時(shí)間： 2017-09-01

  上傳用戶：cuiyashuo

• this is a code of AMBA AHB master protocol in verilog免費(fèi)下載

  資源簡(jiǎn)介：this is a code of AMBA AHB master protocol in verilog

  標(biāo)簽： protocol verilog master this

  上傳時(shí)間： 2017-09-10

  上傳用戶：冇尾飛鉈

• Code ASM for PIC16F628. Use for CNC/Servo Motor. With simulatio in Proteus (7.0)免費(fèi)下載

  資源簡(jiǎn)介：Code ASM for PIC16F628. Use for CNC/Servo Motor. With simulatio in Proteus (7.0)

  標(biāo)簽： for simulatio Proteus Motor

  上傳時(shí)間： 2014-01-06

  上傳用戶：遠(yuǎn)遠(yuǎn)ssad

• * This a software code module for a time-of-day clock object. * The clock may be fixed 12-hour, fi免費(fèi)下載

  資源簡(jiǎn)介：* This a software code module for a time-of-day clock object. * The clock may be fixed 12-hour, fixed 24-hour, or dynamically * configurable between these two types. Clock data can be accessed * as a binary number representing the num...

  標(biāo)簽： clock time-of-day software module

  上傳時(shí)間： 2013-12-07

  上傳用戶：llandlu

• This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs t免費(fèi)下載

  資源簡(jiǎn)介：This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs...

  標(biāo)簽： mixed-timing low-latency interfaces first-out

  上傳時(shí)間： 2015-10-08

  上傳用戶：dapangxie

• 用20個(gè)示例項(xiàng)目的方式介紹Matlab/Simulink。內(nèi)容包括： *Contains over 20 hands-on projects in MATLAB(with code) integra免費(fèi)下載

  資源簡(jiǎn)介：用20個(gè)示例項(xiàng)目的方式介紹Matlab/Simulink。內(nèi)容包括： *Contains over 20 hands-on projects in MATLAB(with code) integrated throughout the book *Includes a complete introduction to Simulink *Accompanied by a CD-ROM containing MATLAB examples, ...

  標(biāo)簽： Contains Simulink hands-on projects

  上傳時(shí)間： 2014-01-03

  上傳用戶：hj_18

• wince6.0平臺(tái)上的任務(wù)管理器,功能類似于windows的任務(wù)管理器. In order to develop applications for Windows Mobile 6.x from免費(fèi)下載

  資源簡(jiǎn)介：wince6.0平臺(tái)上的任務(wù)管理器,功能類似于windows的任務(wù)管理器. In order to develop applications for Windows Mobile 6.x from within Visual Studio 2005 or 2008, you need to download a separate SDK from Microsoft. The SDK also ships with a full f...

  標(biāo)簽： applications develop Windows windows

  上傳時(shí)間： 2017-01-16

  上傳用戶：aappkkee

• The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmwa免費(fèi)下載

  資源簡(jiǎn)介：The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The W78E58B contains a 32K bytes of main ROM a...

  標(biāo)簽： microcontroller programmable in-system W78E58B

  上傳時(shí)間： 2017-04-27

  上傳用戶：yiwen213